During which phase of the fetch-decode-execute cycle does the CPU interpret the fetched instruction?
- Fetch
- Decode
- Execute
- Store
Which register holds the memory address of the instruction about to be used?
- Program counter
- Memory address register
- Memory data register
- Accumulator
Which register stores the data which will be used next?
- Program counter
- Memory address register
- Memory data register
- Accumulator
What is the potential advantage of a dual-core processor over a single-core processor?
- Up to double the clock speed
- Up to double the energy efficiency
- Up to double the processing capacity
- Up to double the cache size
Which type of cache memory is the fastest?
- Level 1
- Level 2
- Level 3
- Level 4
Which level of CPU cache is closest to the processor core and typically the smallest in size?
- L1 cache
- L2 cache
- L3 cache
- RAM
Which architecture allows instructions and data to share the same memory in the fetch-decode-execute cycle?
- RISC architecture
- CISC architecture
- Harvard architecture
- Von Neumann architecture
How many instructions per second can a 3.6GHz CPU process?
- 3,600
- 3,600,000
- 3,600,000,000
- 3,600,000,000,000
Which of the following is considered an input device?
- Printer
- Monitor
- Keyboard
- Speakers
What is the primary function of the fetch-decode-execute cycle in a computer?
- Print documents
- Manage network connections
- Execute program instructions
- Create graphics
